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Between 2026-07-31 11:59 p.m. and 2026-09-01 12:00 a.m.
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I just pushed my design through wafer.space and it took 10 hours. Almost all of the time (8h47m) was spent in esd and sab decks in KLayout DRC. Can this be accelerated? It would be nice to have just to wait for an hour to see the final GDS. Github issue: https://github.com/wafer-space/gf180mcu-project-template/issues/76#issuecomment-5248976075 Thanks, Andreas
Title: KLayout DRC: esd and sab decks each take 4+ hours on a full-chip 0.5x1 padring design Body: Ran the full LibreLane flow (make librelane) for a custom design on the 0p5x1 slot (GF180MCU, gf18...
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